The present invention relates generally to integrated circuit devices and, more particularly, to a method and system for maintaining uniform module junction temperature during burn-in.
Integrated circuits exhibit most failures during early life and at the end of their useful life, and thus tend to be the most reliable between those two periods. Many, if not most, integrated circuit early life failures can be accelerated by increased temperature. Accordingly, integrated circuits utilized in high reliability systems are subjected to burn-in testing by semiconductor manufacturers or independent test labs wherein an integrated circuit is placed in a burn-in oven that produces an in-oven ambient temperature intended to achieve a desired chip junction temperature. Typically, during burn-in testing, the integrated circuit under test is also powered (i.e., power is applied to the supply pins of the integrated circuit). This is also referred to as static burn-in testing. If the integrated circuit is further being operated as intended during the burn-in, then such testing is referred to as dynamic burn-in testing.
In any case, one important consideration with respect to conventional burn-in testing relates to the precise control of the burn-in temperature through control of the oven ambient temperature. More specifically, maintaining a specified chip junction temperature is very difficult due to the lack of knowledge of the specific characteristics of the thermal environment (e.g., ambient-to-package heat transfer and case-to-junction heat transfer), as well as lack of knowledge of the precise chip power dissipation during the burn-in process. Thus, conventional burn-in testing can result in under-screening using temperatures that are too low, or in overstress of the integrated circuit using temperatures that are too high.
Furthermore, variations in the voltage and temperature acceleration of the IC devices may also lead to inadequate stress levels and therefore early-life failures for the target integrated circuit application. Devices that are burned-in at varying voltages and temperatures may not see sufficient stress levels, which can lead to early-life failures in the target application. Accordingly, the burn-in board (BIB) design should ensure that both the voltage supply and temperature levels are met at all of the module locations. However, providing a consistent junction temperature in high thermally resistive packages, such as wire-bond ball grid arrays (BGA) becomes increasingly difficult given that device scaling reduces the active power but increases the standby component of the power and increases the variation across the process window.
For example, an FBGA wire-bond package (having a junction-to-case thermal resistance of about 20° C./W) used in conjunction with an SRAM device having a maximum operating burn-in power of 1 watt will require that the burn-in oven temperature be set at 120° C. to establish a desired junction temperature of 140° C. However, if the operating power of the SRAM varies from 0.2 W to 2.0 W, then the oven set temperature of 120° C. would result in corresponding (and undesirable) junction temperature variations from 124° C. to 160° C.
Accordingly, it would be desirable to be able to maintain a near-constant power characteristic across process variations and to reduce module junction temperature variations during burn-in testing.